1. Field of the Invention
The present invention relates to a technology for driving a display panel including a group of cells as display devices having a memory function, and more particularly to a method for driving a plasma display panel and an apparatus for driving the same which are directed to an improvement in the contrast of an alternating current (AC) type plasma display panel. (Generally, the whole plasma display apparatus inclusive of the plasma display panel and peripheral circuits is referred to as a xe2x80x9cPDPxe2x80x9d.)
The AC type plasma display panel sustains discharge and carries out light emission display by alternately applying voltage waveforms of a plurality of pulses to two electrodes for sustaining this discharge. A discharge (lighting) operation for every discharge period finishes within a few micro-seconds (xcexcs) after the application of pulses. The ions defined as positive electric charges that are generated by this discharge operation are accumulated over an insulating layer on the electrode to which a negative voltage is applied, and electrons defined as negative electric charges are similarly accumulated over an insulating layer on the electrode to which a positive voltage is applied.
Therefore, if wall charges are first generated by causing the discharge by the pulses (write pulses) each having a relatively high voltage (write voltage) and then the pluses (sustain discharge pulses, that is, sustain pulses) each having a voltage lower than that of each of the write pulses (sustain discharge voltage) and an opposite polarity to each of the write pulses are applied to the electrodes, electric charges generated by the sustain pulses are superimposed on the wall charges previously accumulated by the write pulses so as to enhance the accumulated wall charges. As a result, the potential of the wall charges with respect to a discharge space becomes large and, at least, the above voltage exceeds a discharge threshold voltage at which the discharge starts. In other words, given cells that once effected the write discharge and have formed the wall charges have the characteristics that these cells sustain the discharge when the sustain discharge pulses are alternately applied thereto in opposite polarities. A phenomenon having the above characteristics is referred to as a xe2x80x9cmemory effectxe2x80x9d or xe2x80x9cmemory drivexe2x80x9d. The AC type plasma display panel carries out the display by utilizing this memory effect.
2. Description of the Related Art
The AC type plasma display panels can be classified into a two-electrode type which effects selective discharge (addressing discharge) and the sustain discharge by using two electrodes and a three-electrode type which effects addressing discharge by using a third electrode. In color plasma display panels for carrying out multi-gradation display, a phosphor inside the cells is excited by ultra-violet rays generated due to the discharge between different kinds of electrodes, but this phosphor involves the problem that it is extremely fragile against the impact of the ions defined as the positive charges that are generated simultaneously by the discharge. The former two-electrode type plasma display panel described above employs the construction in which the ions are allowed to collide directly with the phosphor and for this reason, the life of the phosphor is likely to become shortened. To avoid this problem, therefore, the latter three-electrode type plasma display panel utilizing a surface-discharge (that is, surface-discharge type plasma display panels) which is carried out between different electrodes that are located in the same plane, has been generally used in color plasma display panels.
Recently, an interlace system three-electrode type AC plasma display panel which is capable of providing a high definition display screen by reducing the pixel pitch (i.e., a space between adjoining cells) has recently attracted special attention. The method for driving the plasma display panel according to the prior art, etc, will be explained hereby with reference to FIGS. 1 to 9 that will be mentioned in the later-appearing xe2x80x9cBRIEF DESCRIPTION OF THE DRAWINGSxe2x80x9d in order to have the plasma display panel and its driving method according to the prior art more easily understood. The conventional method for driving the interlace system plasma display panel, etc, is typically described in Japanese Unexamined Patent Publication No. 9-160525 and No. 10-207417 corresponding to Japanese Patent Application No. 9-12700 filed on Jan. 27, 1997 by the same applicant (Fujitsu) as for the present invention. Such a driving method is referred to as the xe2x80x9cAlisxe2x80x9d (Alternate Lighting of Surfaces) method.
In a plasma display panel 10 having a schematic construction of a conventional surface-discharge type plasma display panel shown in FIG. 1, pixels are represented by dotted lines for only the display line (display row) L1. To simplify the explanation, the number of pixels of the plasma display panel 10 is assumed hereby as 6xc3x978=48 in terms of the monochromatic pixels. Incidentally, the present invention can be applied to both color display and monochromatic display, and one pixel of the color display corresponds to three pixels of the monochromatic display.
In order to facilitate the production of the plasma display panel and to provide high definition by reducing the pixel pitch, the plasma display panel 10 employs the construction in which the partitions in the row direction are removed from the conventional plasma display panels. To prevent the occurrence of the erroneous discharge due to influences between the adjacent display lines resulting from the removal of the partition, interlace scanning is carried out so that the voltage waveforms of the sustain pulses have mutually opposite phases between the odd-numbered rows and the even-numbered rows of the electrodes for surface-discharge as will be described later.
In FIGS. 2 and 3, a perspective view showing the state in which the opposing gap between the color pixels 10a of the plasma display panel shown in FIG. 1 is expanded and a longitudinal sectional view along a sustain electrode X1 of the color pixel 10a, is illustrated, respectively.
In FIGS. 2 and 3, transparent electrodes 121 and 122 of an ITO film, or the like, are disposed in parallel with each other on one of the surfaces of a glass substrate 11, and metal electrodes 131 and 132 of copper (Cu), or the like, are formed along the center line on the transparent electrodes 121 and 122 in order to reduce the voltage drop in the longitudinal direction of the transparent electrodes 121 and 122, respectively. The transparent electrode 121 and the metal electrode 131 together constitute the sustain electrode X1 while the transparent electrode 122 and the metal electrode 132 together constitute the scan electrode Y1. A dielectric member 14 for retaining the wall charges is deposited on the glass substrate 11 and the electrodes X1 and Y1, and an MgO protective film 15 is further deposited on the dielectric member 14.
Address electrodes A1, A2 and A3 and partitions 171 to 173 for partitioning these address electrodes are formed on the surface of the glass substrate 16 that opposes the MgO protective film 15 in the direction orthogonally crossing the sustain electrode X1 and the sustain electrode Y1. These partitions define discharge cells (which are also referred to merely as the xe2x80x9ccellsxe2x80x9d or xe2x80x9cslitsxe2x80x9d) in the regions where the addressing electrodes cross the sustain electrodes and the scan electrodes. A phosphor 181 emitting red light, a phosphor 182 emitting green light and a phosphor 183 emitting blue light when ultraviolet rays generated by the discharge are incident to them are deposited between the partitions 171 and 172, between the partitions 172 and 173 and between the partitions 173 and 174, respectively. A Ne+Xe Penning mixed gas, for example, is sealed into the discharge space between these phosphors 181 to 183 and the MgO protective film 15.
The partitions 171 to 174 function as spacers for preventing the ultra-violet rays generated by the discharge from being incident to the adjacent pixels and also for forming the discharge space. When the phosphors 181 to 183 are made of the same material, the plasma display panel 10 is a display panel for monochromatic display.
In an apparatus for driving a plasma display panel using the plasma display panel shown in FIG. 1, there are disposed a driving circuit for supplying a plurality of kinds of driving voltage pulses, that are necessary for writing predetermined display data to the selected cells, the sustain electrode, the scan electrode and the addressing electrode, and a control circuit for controlling the sequence of the supply of these driving voltage pulses. The driving circuit includes odd- and even-numbered X sustain circuits for supplying the write pulses and the sustain pulses to the sustain electrodes X1 to X5, odd- and even-numbered Y sustain circuits for supplying the scan pulses and the sustain pulses to the scan electrodes Y1 to Y4 and an addressing circuit for supplying the addressing pulses to the addressing electrodes A1 to A6.
In FIG. 4, a structural example of a frame for forming the color images of the plasma display panel shown in FIG. 1, is illustrated. In FIGS. 5A and 5B, a sequence of display scanning in the addressing period of the frame shown in FIG. 4, is illustrated.
The frame shown in FIG. 4 is divided into two fields, that is, an odd-numbered field and an even-numbered field. Each field comprises first to third subfields. In each sub-field of the odd-numbered field, the voltage having the waveform shown in the later-appearing FIG. 6 is supplied to each electrode of the plasma display panel 10 so as to cause the display lines L1, L3, L5 and L7 to display, and in each sub-field of the even-numbered field, the voltage having the waveform shown in the later-appearing FIG. 7 is supplied so as to enable the display lines L2, L4, L6 and L8 shown in FIG. 1 to display. The sustain discharge periods in the first to third sub-fields are T1, 2T2 and 4T1, respectively, and the sustain discharge is effected a number of times proportional to the length of the period in each sub-field. Consequently, the luminance has 8 (eight) kinds of gradations. Similarly, when the number of the sub-fields is 8 and the ratio of the sustain discharge periods is 1:2:4:8:16:32:64:128, the luminance has 256 kinds of gradations.
Scanning of the display lines in the addressing period is carried out in the number of sequence inside the white circle ◯ in FIG. 5A. In other words, the display lines are scanned in the sequence of L1, L3, L5 and L7 in the odd-numbered fields, and are scanned in the sequence of L2, L4, L6 and L8 in the even-numbered fields. Further, to reduce power consumption in the addressing period, it is possible to further divide each of the display lines L1, L3, L5 and L7 inside the odd-numbered fields into odd-numbered rows and even-numbered rows, and to scan serially one of these rows first and then to scan the other, as shown in FIG. 5B. This also holds true of the even-numbered fields.
In FIG. 6, the waveforms of the voltages applied to the electrodes in the odd-numbered fields in the first example of a conventional method for driving the plasma display panel, is illustrated. In FIG. 7, the waveforms of the voltages applied to the electrode in the even-numbered fields in the first example of the conventional method for driving the plasma display panel. Though the odd-numbered field and the even-numbered field have a plurality of sub-fields having mutually different sustain discharge periods in practice as shown in FIG. 4, the drawings show only one sub-field to simplify the related explanation.
First, a series of operations in the odd-numbered field will be explained with reference to FIG. 6. Symbols W, E, A and S in FIG. 6 represent the points of time in which the whole surface write discharge for all the cells, the whole surface self-erase discharge for all the cells, the addressing discharge and the sustain discharge occur, respectively. To simplify the explanation, the electrodes will be generically called as follows.
Sustain electrode (i.e. X electrode): electrodes X1 to X5 Odd-numbered sustain electrode: electrodes X1, X3 and X5 Even-numbered sustain electrode: electrodes X2 and X4 Scan electrode (i.e. Y electrode): electrodes Y1 to Y4 Odd-numbered scan electrode: electrodes Y1 and Y3 Even-numbered scan electrode: electrodes Y2 and Y4 Addressing electrode: addressing electrodes A1 to A6
On the other hand, symbols have the following meaning.
Vfxy: discharge start voltage between adjacent sustain electrode and scan electrode
Vfay: discharge start voltage between opposed addressing electrode and scan electrode
Vwall: voltage between positive wall charges and negative wall charges (wall voltage) due to wall charges generated by discharge between the adjacent sustain electrode and scan electrode
Typically, Vfxy=290V and Vfay=180V. Further, the voltage between the addressing electrode and the sustain electrodes is abbreviated as the voltage between the A-X electrodes and the voltage between the addressing electrode and the scan electrodes is abbreviated as the voltage between A-Y electrodes. Similar abbreviation will be used between other electrodes, too.
(1) Reset period
During the reset period, the voltage waveforms supplied to the sustain electrodes are the full surface write pulse (which is generally called the xe2x80x9cwrite pulsexe2x80x9d) and are mutually the same, the voltage waveforms supplied to the scan electrodes are 0V and are mutually the same, and the voltage waveforms supplied to the addressing electrodes are an intermediate voltage pulse and are mutually the same.
First, the applied voltage of each electrode is 0V. The positive wall charge exists on the lighting cells (pixels), that is, the MgO protective film 15 of the display slit on the sustain electrode side and the negative wall charge exists on the side of the scan electrodes (that is, the wall charges of the positive polarity remains) due to the last sustain pulse of the previous sustain discharge period of the reset period. The wall charges hardly exist on the side of the sustain electrode and on the side of the scan electrode of the cells which are in a lights-out state (i.e., an off state), that is, non-display slits.
The reset discharge pulse having a voltage Vw (that is, the write pulse) is supplied to the sustain electrode and an intermediate voltage pulse having a voltage Vaw is supplied to the addressing electrode during the period axe2x89xa6txe2x89xa6b. For example, Vw=310V and Vw greater than Vfxy. The whole surface write discharge for all the cells W (which is also called xe2x80x9call cell write dischargexe2x80x9d because the above write discharge is effected for all the cells irrespective of the lighting cells and the lights-out cells) between the adjacent X-Y electrodes, that is, between the X-Y electrodes of the display lines L1 to L8 irrespective of the existence of the wall charges. The wall charges having the opposite polarity (that is, the negative wall charges) occur as the resulting electrons and positive ions are extracted by the electric field due to the X-Y electrode voltage Vw, so that the field intensity of the discharge space decreases and the discharge finishes within one to several micro-seconds (xcexcs). Because the voltage Vaw is approximately Vw/2 and also because the voltage between the A-X electrodes and the voltage between the A-Y electrodes have mutually opposite phases but have a substantially equal absolute value, the average of the wall charges adhered to the phosphor by the discharge is substantially zero (0).
When the reset discharge pulse falls at t=b, that is, when the applied voltage having the opposite polarity to the wall voltage disappears, the wall voltage Vwall between the X-Y electrodes becomes larger than the discharge start voltage Vfxy, and the whole surface self-erase discharge E (which is also called xe2x80x9call cell self-erase discharge) occurs. In this instance, since the voltages of the sustain electrode, the scan electrode and the addressing electrode are 0V, it would be ideal that the wall charge is hardly generated by this whole surface self-erase discharge and the ions and the electrons are recombined with each other inside the discharge space to thereby accomplish complete neutralization. In practice, however, all the wall charges are not always neutralized completely in the whole surface self-erase discharge and a small amount of the wall charges having the negative polarity remain in the cells.
(2) Addressing period
In the addressing period, the voltage waveforms supplied to the odd-numbered sustain electrodes are mutually the same and the voltage waveforms supplied to the even-numbered sustain electrodes are mutually the same. Further, the voltage waveforms supplied to the non-selected scan electrodes are a voltage xe2x88x92Vsc and are mutually the same. The scan electrodes are selected in the order of Y1 to Y4, and a scan pulse having a voltage xe2x88x92Vy (that is, a scan pulse) is supplied to the selected scan electrodes while the non-selected scan electrodes are set to a voltage xe2x88x92Vsc. For example, Vsc=Vaxe2x88x9250V and Vy 4xe2x88x92150V.
In the condition (cxe2x89xa6txe2x89xa6d), the scan pulse of the voltage xe2x88x92Vy is supplied to the scan electrode Y1, and the addressing pulse of a voltage Va is supplied to the addressing electrodes of the cells required to be turned on. In this case, the relation Va+Vy greater than Vfay is established, and the addressing discharge occurs for only the cells required to be turned on, the wall charges having the opposite polarity occurs and the discharge finishes. At the time of this addressing discharge, the pulse of the voltage Vx is supplied to only the electrode X1 among the electrodes X1 and X2 adjacent to the electrode Y1. When the discharge start voltage between the X-Y electrodes triggered by this addressing discharge is Vxyt, the following relation is established:
Vx+Vsc less than Vxyt less than Vx+Vy less than Vfxy
The write discharge occurs between the X1-Y1 electrodes of the display line L1 and the wall charges of the opposite polarity, to an extent such that self discharge does not occur, are generated between the X1-Y1 electrodes and the discharge finishes. On the other hand, no discharge develops between the X2-Y2 electrodes of the display line L2.
In the condition (dxe2x89xa6txe2x89xa6e), the scan pulse of a voltage of xe2x88x92Vy is supplied to the electrode Y2, the pulse of the voltage Vx is supplied to the even-numbered sustain electrodes and the address pulse of the voltage Va is supplied to the addressing electrodes for the cells required to be turned on. Similarly, the write discharge occurs between the X2-Y2 electrodes of the display line L3, the wall charges of the opposite polarity are generated but no discharge develops between the X3-Y2 electrodes of the display line L4.
An operation similar to the above is thereafter executed in the same way at exe2x89xa6txe2x89xa6g.
The write discharge of the display data develops for the cells required to be turned on in the order of the display lines L1, L3, L5 and L7 and the positive wall charges are generated on the side of the scan electrode while the negative wall charges are generated on the side of the sustain electrode. In other words, the positive wall charges are generated in the selected cells (display slits) but no wall charges are generated in the non-selected cells (non-display cells).
(3) Sustain discharge period
A series of sustain pulses having the same phase and the same voltage Vs are supplied to the odd-numbered sustain electrodes and to the even-numbered scan electrodes during the sustain discharge period, and a series of sustain pulses having a phase deviated by 180xc2x0 (xc2xd cycle) from the former series are supplied to the even-numbered sustain electrodes and to the odd-numbered scan electrodes. On the other hand, the voltage Ve is supplied to the addressing electrodes in synchronism with the rising edge of the first sustain pulse and is held until the sustain discharge period is completed.
In the condition (h greater than t greater than p), the sustain pulse of the voltage Vs is supplied to the odd-numbered scan electrodes and the even-numbered sustain electrodes. The effective voltage of the cells between the odd-numbered electrodes Y and the odd-numbered electrodes X is Vs+Vwall, and the effective cell voltage between the even-numbered X-Y electrodes is Vsxe2x88x92Vwall. Further, the effective cell voltages between the odd-numbered X and even-numbered scan electrodes and between the even-numbered X and odd-numbered scan electrodes are 2Vwall, respectively. In this case, the following relation is established:
Vs less than Vfxy less than Vs+Vwall, 2Vwall less than Vfxy
The sustain discharge occurs between the odd-numbered Y electrodes and the odd-numbered X electrodes, the wall charges of the opposite polarity develop and the discharge finishes. No sustain discharge occurs between other electrodes. Therefore, the display is effective in only the odd-numbered display lines L1 and L5 inside the odd-numbered fields. The sustain discharge does not occur only this first time between the even-numbered Y electrodes and the even-numbered X electrodes.
In the condition (qxe2x89xa6txe2x89xa6r), the sustain pulse of the voltage Vs is supplied to the odd-numbered sustain electrodes and to the even-numbered scan electrodes. The effective voltages of the cells between the odd-numbered X and odd-numbered Y electrodes and between the even-numbered Y and even-numbered x electrodes are all Vs+Vwall, and the effective voltages between the odd-numbered Y and even-numbered X electrodes and between the odd-numbered X and even-numbered Y electrodes are zero. Consequently, the sustain discharge occurs between the odd-numbered X and odd-numbered Y electrodes and between the even-numbered Y and even-numbered X electrodes, and the wall charges having the opposite polarity occur, so that the discharge finishes. Therefore, display of all the odd-numbered display lines L1, L3, L5 and L7 of the odd-numbered fields becomes simultaneously effective.
Thereafter, the sustain discharge is repeated in the same way. In this case, as is obvious from the wall charges shown in FIG. 6, the effective voltages of the cells between the odd-numbered Y and even-numbered X electrodes of the non-display lines and between the odd-numbered X and even-numbered Y electrodes become zero. The last sustain discharge of the sustain discharge period is effected so that the polarity of the wall charges can return to the original state.
Next, the operation in the even-numbered fields will be explained. In FIG. 7, display of the display lines L1, L3, L5 and L7 of the pairs of the scan electrodes Y1 to Y4, and the sustain electrodes X1 to X4 respectively adjacent to the above scan electrodes in the upper positions, becomes effective in the odd-numbered fields as described above. In the even-numbered fields, display of the display lines L2, L4, L6 and L8 of the pairs of the electrodes Y1 to Y4, and the electrodes X2 to X5 respectively adjacent to the above scan electrode in the lower positions, may be effected. This can be accomplished by reversing the role of the electrode X1 and the electrode X2 for the electrode Y1, reversing the role of the electrode X2 and the electrode X3 for the electrode Y2, and so forth. In other words, the voltage waveforms supplied to the odd-numbered sustain electrodes and the even-numbered sustain electrodes that are grouped may be replaced with each other. FIG. 7 shows the waveforms of the voltages applied to the electrode in the even-numbered fields.
The operation in the even-numbered fields is obvious from the explanation given above and from FIG. 7. Generally speaking, the whole surface write discharge W and the whole surface self-erase discharge E are carried out in the reset period, the electrodes Y1 to Y4 are serially selected and the write discharge of the display data is effected in the order of the display lines L2, L4, L6 and L8 in the addressing period, and the simultaneous sustain discharge of these display lines L2, L4, L6 and L8 is repeated in the sustain discharge period.
Referring further to FIGS. 6 and 7, power consumption can be reduced if the number of pulses can be reduced. The number of pulses can be reduced if the pulses supplied to the odd-numbered sustain electrodes and the even-numbered sustain electrodes are rendered continuous during the addressing period. This can be accomplished by employing the arrangement shown in FIG. 5(B) for the scanning sequence. In other words, the display lines L1, L3, L5 and L7 inside the odd-numbered fields are further divided into the odd-numbered rows and the even-numbered rows, and after one of them is serially scanned, the other may be scanned. This also holds true of the even-numbered fields.
In the first example of the conventional interlace system plasma display panel driving method described above, the whole surface write discharge and the self-erase discharge are carried out every time in the reset period of each sub-frame and are not dependent on whether or not the sustain discharge is effected in the sustain discharge period immediately before this period. Therefore, background light emission becomes unnecessarily large and the contrast ratio is likely to decrease.
In FIGS. 8 and 9, timing charts useful for explaining the second example of a conventional interlace system plasma display driving method worked out in consideration of the problem described above, are illustrated.
FIGS. 8 and 9 show the waveforms of one frame comprising the odd-numbered fields and the even-numbered fields. Though the odd-numbered field and the even-numbered field have, in practice, a plurality of sub-fields having mutually different sustain discharge periods as shown in FIG. 4, the drawings show only one sub-field to simplify the illustration.
Each sub-field has the reset period, the addressing period and the sustain discharge period as shown in the drawings. When the immediately previous sub-field finishes, the wall charge corresponding to the display of this sub-field remains, and the reset discharge is conducted in the reset period at the start of the next sub-field. This reset discharge is a strong discharge which is generated by applying a voltage exceeding the discharge start voltage between the sustain electrode Xi (where i is a given natural number) and the scan electrode Yn (where n is a given natural number), and makes uniform the charge distribution of each discharge cell irrespective of the discharge state in the immediately previous sub-field. The second example of the prior art sets the potential of each electrode to a level exceeding the discharge start voltage for the display slits and to a level less than the discharge start voltage for the non-display slits.
To begin with, the operation in the odd-numbered fields shown in FIGS. 8 and 9 will be explained. In the odd-numbered field, the positive pulse Vs is applied to the odd-numbered sustain electrodes X1, X3, . . . , X2ixe2x88x921 (where i is a given natural number) and a negative pulse xe2x88x92Vu is applied to the odd-numbered scan electrodes Y1, Y2, . . . , Y2nxe2x88x921 (where n is a given natural number). At the same time, the negative pulse xe2x88x92Vu is applied to the even-numbered sustain electrodes X2, X4, . . . , X2I whereas the positive pulse Vs is applied to the Y2, Y4, . . . , Y2n. As a result, the potential difference between the odd-numbered sustain electrodes and the scan electrodes X1-Y1, X3-Y3, . . . , X2ixe2x88x921-Y2nxe2x88x921 as the display slits in the odd-numbered field and the even-numbered sustain electrodes and scan electrodes X2-Y2, X4-Y4, . . . , X2ixe2x88x92I-Y2n become Vs+Vu. When this potential difference Vs+Vu is set to a potential higher than the discharge start voltage between the electrodes, the reset discharge is effected in each display slit. On the other hand, the potential difference between the odd-numbered scan electrodes and the even-numbered sustain electrodes as the non-display slits in the odd-numbered fields, i.e. Y1-X2, Y3-X4, . . . , Y2nxe2x88x921-X2i is zero, and no discharge occurs. Therefore, in the second conventional example described above, the reset discharge is effected in only the display slits.
Incidentally, it has been customary to apply the pulse Vaw to the addressing electrodes with the application of the whole surface write pulse, but the application of this pulse Vaw becomes unnecessary, because the voltage applied to each sustain electrode and to each scan electrode becomes lower than in the prior art and a possibility of the occurrence of the discharge with the addressing electrodes does not exist.
Due to the reset discharge described above, the wall charges having the mutually opposite polarities are accumulated in excess on both the sustain electrode and the scan electrode. Therefore, the self-erase discharge occurs due to the wall charges themselves by setting the potentials of both electrodes to an equal voltage or more concretely, by setting both electrodes to the ground potential, to thereby neutralize the wall charges.
In the subsequent addressing period, the write discharge corresponding to the input data, that in turn corresponds to the display data, is effected. Here, a method is employed which first executes the write operation of the odd-numbered electrodes and then executes the write operation of the even-numbered electrodes. In other words, the scan pulse xe2x88x92Vy is serially applied to the odd-numbered electrodes Y1, Y3, . . . , Y2nxe2x88x921. Incidentally, the base pulse xe2x88x92Vsc is applied to each scan electrode Yn during the addressing period, and the scan pulse xe2x88x92Vy is superposed with the base pulse xe2x88x92Vsc. The addressing pulse Va is selectively applied to the addressing electrode Aj (where j is a given natural number) in accordance with the input signal, and the discharge is effected between this addressing electrode and the scan electrode Y2nxe2x88x921 to which the scan pulse xe2x88x92Vy is applied. In this instance, since the pulse Vx is applied to only the odd-numbered sustain electrodes X1, X3, . . . , X2ixe2x88x921 in the odd-numbered fields, the write discharge is effected only between the odd-numbered sustain electrodes and scan electrodes X1-Y1, X3-Y3, X2ixe2x88x921-Y2nxe2x88x921, and the wall charges are built up on both electrodes. Next, the scan pulse xe2x88x92Vy is serially applied to the even-numbered scan electrodes Y2, Y4, . . . , Y2n. Similarly, the data pulse Va is selectively applied to the addressing electrodes Aj and the pulse Vx is applied this time to only the even-numbered sustain electrodes X2, X4, . . . , X2i. Consequently, the discharge is effected between only the even-numbered sustain electrodes and scan electrodes X2-Y2, X4-Y4, . . . , X2i-Y2n, and the wall charges are accumulated on both electrodes.
In the subsequent sustain discharge period, the sustain discharge pulse Vs is alternately applied to the sustain electrodes Xi and the scan electrodes Yn constituting the display slits, so that the sustain discharge is executed in the discharge cells in which the write discharge is effected. In this instance, the voltage pulse having the same phase is applied to the sustain electrodes and the scan electrodes constituting the non-display slits lest the discharge occurs between the sustain electrodes and the scan electrodes constituting the non-display slits. In other words, the sustain discharge pulse is alternately applied in the odd-numbered fields between the odd-numbered sustain electrodes and scan electrodes X1-Y1, X3-Y3, . . . , X2ixe2x88x921-Y2nxe2x88x921 and between the even-numbered sustain electrodes and scan electrodes X2-Y2, X4-Y4, . . . , X2i-Y2n constituting the display slits, but this pulse has the same phase between the odd-numbered scan electrodes and the even-numbered sustain electrodes Y1-X2, Y3-X4, . . . , Y2nxe2x88x921-X2i and between the even-numbered scan electrodes and the odd-numbered sustain electrodes Y2-X3, Y4-X5, . . . , Y2n-X2ixe2x88x921 constituting the non-display slits.
Next, in the even-numbered fields, the display slits are so changed as to be positioned between the odd-numbered scan electrodes and the even-numbered sustain electrodes Y1-X2, Y3-X4, . . . , Y2nxe2x88x921-X2i and between the even-numbered scan electrodes and the odd-numbered sustain electrodes Y2-X3, Y4-X5, Y2n-X2ixe2x88x921. The impressed voltage to each display slit is the same as that of the odd-numbered field. In other words, the positive pulse Vs is applied this time to the odd-numbered scan electrodes Y1, Y3, . . . , Y2nxe2x88x921 while the negative pulse xe2x88x92Vu is applied to the even-numbered sustain electrodes X2, X4, . . . , X2i. At the same time, the negative pulse xe2x88x92Vu is applied to the even-numbered scan electrodes Y2, Y4, . . . , Y2n while the positive pulse Vs is applied to the odd-numbered sustain electrodes X1, X3, . . . , X2 ixe2x88x921. In consequence, the voltage differences between the odd-numbered scan electrodes and the even-numbered sustain elctrodes Y1-X2, Y3-X4, . . . , Y2nxe2x88x921-X2i and between the even-numbered scan electrodes and the odd-numbered sustain electrodes Y2-X3, Y4-X5, . . . , Y2n-X2ixe2x88x921 as the display slits in the even-numbered fields become Vs+Vu that exceeds the discharge start voltage between these electrodes, and the reset discharge is executed in each display slit.
On the other hand, the potential difference between the odd-numbered sustain electrodes and scan electrodes X1-Y1, X3-Y3, . . . , X2xe2x88x921-Y2nxe2x88x921 and the even-numbered sustain electrodes and scan electrodes X2-Y2, X4-Y4, . . . , X2-Y2n as the non-display slits in the even-numbered fields are both zero and no discharge occurs. Therefore, the reset discharge is executed in only the display slits. After this reset discharge is completed, the self extinction discharge occurs in the same way as in the odd-numbered fields, and the wall charges generated by the reset discharge are neutralized.
In the subsequent addressing period, too, the driving sequence is executed in the same way as in the odd-numbered fields described above with the exception that the display slits are changed. Therefore, the detailed explanation of the driving sequence in the addressing period in the even-numbered fields will be hereby omitted.
In the subsequent sustain discharge period, too, the sustain discharge pulse Vs is alternately applied to the sustain electrodes and the scan electrodes constituting the display slits in the same way as in the case of the odd-numbered fields described above, and the sustain discharge is executed in the discharge cells in which the write discharge is effected. Therefore, the detailed explanation of the driving sequence in the sustain discharge period in the even-numbered fields, too, will be hereby omitted.
As described above, according to the first example of the conventional driving method of the interlace system plasma display panel, the full surface write discharge and the self-erase discharge are executed every time for all the slits during the reset period of each sub-frame irrespective of the display slits (that is, the slits between the sustain electrodes that have executed the sustain discharge and the scan electrodes) and the non-display slits (that is, the slits between the sustain electrodes that have not executed the sustain discharge and the scan electrodes). Therefore, background light emission becomes larger than necessary level and the contrast ratio decreases, accompanied by the deterioration of display quality. Further, according to the second example of the conventional driving method of the interlace system plasma display panel, the voltage of the reset discharge pulse is so set as to exceed the discharge start voltage by only the display slits. Therefore, the decrease in the contrast ratio due to the unnecessary reset discharge in the non-display slits can be avoided.
However, even when the second example of the conventional plasma display panel driving method is employed, there is no alteration in that the whole surface write discharge and the self-erase discharge are executed every time in the reset period of each sub-frame and for this reason, a drastic improvement in the contrast ratio cannot be expected.
In view of the problems described above, it is an object of the present invention to provide a method for driving a plasma display panel, and an apparatus for driving the same, which can improve display quality by improving a contrast ratio of a display screen of a plasma display panel, and can guarantee a stable discharge of a next field when a given field is changed to another field.
When driving a plasma display panel comprising a plurality of sustain electrodes and a plurality of scan electrodes disposed in parallel with each other on a substrate for each display line; a plurality of addressing electrodes isolated electrically from the sustain electrodes and the scan electrodes and disposed in so as to cross the sustain electrodes and the scan electrodes; and discharge cells formed in areas in which the addressing electrodes cross the sustain electrodes and the scan electrodes, a method for driving a plasma display panel according to the present invention includes odd-numbered fields for carrying out display between odd-numbered sustain electrodes and odd-numbered scan electrodes and between even-numbered sustain electrodes and even-numbered scan electrodes, and even-numbered fields for carrying out display between the odd-numbered sustain electrodes and the even-numbered scan electrodes and between the even-numbered sustain electrodes and the odd-numbered scan electrodes.
Further, in the driving method described above, each of the odd-numbered and even-numbered fields includes a reset period for applying a predetermined voltage to the sustain electrode, the scan electrode and the addressing electrode and executing a reset discharge in a plurality of discharge cells in order to make uniform a charge distribution among a plurality of discharge cells uniform; an addressing period for executing a write discharge between the scan electrode and the addressing electrode in a selected one of discharge cell and executing a selective write operation in accordance with display data; and a sustain discharge period for applying alternately a sustain discharge pulse to the sustain electrode and the scan electrode in order to repeatedly execute discharge light emission for displaying the display data in the discharge cell in which the selective write operation is executed in the addressing period.
In the driving method of the plasma display panel described above, a reset discharge pulse having a voltage higher than a discharge start voltage necessary for starting the reset discharge is applied in the reset period to the sustain electrode and the scan electrode for the period in which the discharge is started in the discharge cell that has executed the sustain discharge and the discharge cells adjacent to the former discharge cell, and then the potential difference between the sustain electrode and the scan electrode is made substantially zero so that an erase discharge can be done for the cells that have executed the sustain discharge.
Preferably, in the driving method according to the present invention, the time for applying the reset discharge pulse having a voltage higher than the discharge start voltage is set to a value not larger than 2 xcexcs.
Preferably, further, in the driving method according to the present invention, an auxiliary erase pulse having a gentle slope is applied to the sustain electrode or the scan electrode after the passage of the period in which the potential difference between the sustain electrode and the scan electrode is made substantially zero.
Preferably, further, in the driving method according to the present invention, the auxiliary erase pulse described above is set to a pulse having a polarity opposite to that of the reset discharge pulse having a voltage higher than the discharge start voltage.
Preferably, further, in the driving method according to the present invention, the auxiliary erase pulse is a pulse having the opposite polarity to that of the voltage pulse having a voltage higher than the discharge start voltage.
Preferably, further, in the driving method of the present invention, the auxiliary erase pulse is a pulse having the same polarity as that of the pulse having a voltage higher than the discharge start voltage, and is applied to the sustain electrode or scan electrode different from the electrode to which the reset discharge pulse having a voltage higher than the discharge start voltage is applied.
Preferably, further, in the driving method of the present invention, the reset discharge pulse having a voltage higher than the discharge start voltage is applied to either one of the sustain electrode and the scan electrode.
Preferably, further, in the driving method according to the present invasion, the reset discharge pulses having a voltage higher than the discharge start voltage are applied at the same timing.
Preferably, further, in the driving method according to the present invention, a first sustain voltage pulse, which has an opposite polarity to that of the reset discharge pulse having a voltage higher than the discharge start voltage and has a width larger than that of the sustain discharge pulse described above, is applied before the reset discharge pulse having a voltage higher than the discharge start voltage is applied.
Preferably, further, in the driving method according to the present invention, a second sustain voltage pulse having a width larger than that of the sustain discharge pulse is applied for every other display line between the sustain discharge period and the first sustain voltage pulse applied before the application of the reset discharge pulse having a voltage higher than the discharge start voltage.
In the driving method according to the present invention, further, each of the odd- and even-numbered fields includes a reset period in which a predetermined voltage is applied to the sustain electrode, the scan electrode and the addressing electrode in order to make uniform the charge distribution among a plurality of discharge cells and to execute the reset discharge in each of a plurality of discharge cells; an addressing period in which the write discharge is executed in the selected discharge cell between the scan electrode and the addressing electrode and the selective write operation is made in accordance with the display data; and a sustain discharge period in which the sustain discharge pulse is alternately applied to the sustain electrode and the scan electrode in order to repeatedly execute discharge light emission for displaying the display data in the discharge cell in which the selective write operation is made in the addressing period.
When the odd-numbered field and the even-numbered field are switched over to each other, a reset process is executed so that the whole surface write discharge is executed by applying the reset discharge pulse having a voltage higher than the discharge start voltage to the pair of the sustain electrode and the scan electrode, that has executed, or is to execute, the sustain discharge and the self-erase discharge is effected at the point of time in which the reset discharge pulse having a voltage higher than the discharge start voltage is eliminated, and after this reset process is executed, another reset process is executed so that a voltage having the opposite polarity to that of the voltage of the whole surface write discharge and approximate to the sustain discharge pulse is applied for a period larger than the width of the sustain discharge pulse and furthermore, the reset discharge pulse having a voltage higher than the discharge start voltage is applied in the pair of the sustain electrode and the scan electrode that is to effect the sustain discharge in the next odd-numbered field or even-numbered field to thereby execute the whole surface write discharge, and the self-erase discharge is executed at the point of time in which the reset discharge pulse having a voltage higher than the discharge start voltage is eliminated.
Preferably, in the driving method according to the present invention, after the reset process described above is executed for the pair of the sustain electrode and the scan electrode of either one of the odd-numbered and even-numbered display lines among the pairs of the sustain electrodes and the scan electrodes that have executed, or are to execute, the sustain discharge, the reset process is executed for the other pair of the sustain electrode and the scan electrode, the voltage having the opposite polarity to that of the whole surface write discharge in the reset process described above and approximate to the voltage of the sustain discharge pulse is applied for a period at least equal to the pulse width of the sustain discharge pulse, the reset process is further applied to the pair of the sustain electrode and the scan electrode of either one of the odd-numbered and even-numbered display lines in the next odd-numbered field or the next even-numbered field, and then the reset process is executed for the other pair of the sustain electrode and the scan electrode.
On the other hand, in a plasma display panel including a plurality of sustain electrodes and a plurality of scan electrodes disposed in parallel with each other for each display line on a substrate, a plurality of addressing electrodes electrically isolated from the sustain electrodes and the scan electrodes and disposed so as to cross the sustain electrodes and the scan electrodes and discharge cells formed in areas in which the addressing electrodes cross the sustain electrodes and the scan electrodes, respectively, an apparatus for driving a plasma display panel according to the present invention includes odd-numbered fields for carrying out display between odd-numbered sustain electrodes and odd-numbered scan electrodes and between even-numbered sustain electrodes and even-numbered scan electrodes, respectively, and even-numbered fields for carrying out display between the odd-numbered sustain electrodes and the even-numbered scan electrodes and between the even-numbered sustain electrodes and the odd-numbered scan electrodes, respectively.
In the driving apparatus described above, each of the odd-numbered and even-numbered fields includes a reset period for executing a reset discharge inside a plurality of discharge cells by applying a predetermined voltage to the sustain electrodes, the scan electrodes and the addressing electrodes in order to make uniform the charge distribution among a plurality of discharge cells; an addressing period in which a write discharge is effected between the scan electrode and the addressing electrode in a selected discharge cell, and executing a selective write operation; and a sustain discharge period in which a sustain discharge pulse is alternately applied to the sustain electrode and the scan electrode in order to repeatedly execute discharge light emission for displaying display data in the discharge cell in which the selective write operation is effected in the addressing period described above.
Here, the apparatus for driving the plasma display panel according to the present invention includes driving means for supplying a reset discharge pulse for the reset discharge described above, an addressing pulse for effecting the write discharge described above and a sustain discharge pulse for effecting the sustain discharge to the sustain electrode, the scan electrode and the addressing electrode; and control means for controlling the sequence for supplying the reset discharge pulse, the addressing pulse and the sustain discharge pulse. The control means applies the reset discharge pulse having a voltage higher than a discharge start voltage necessary for starting the reset discharge to the sustain electrode or the scan electrode in the reset period for a period of time in which the discharge is started in only the discharge cell that has executed the sustain discharge and to the discharge cells adjacent to the discharge cell that has executed the sustain discharge, and in this way, makes the potential difference between the sustain electrode and the scan electrode substantially zero, so that an erase discharge can be executed for at least the cell that has executed the sustain discharge.
Further, the apparatus for driving the plasma display panel according to the present invention includes driving means for supplying a reset discharge pulse for effecting a reset discharge, the addressing pulse for effecting a write discharge and a sustain discharge pulse for effecting a sustain discharge to the sustain electrode, the scan electrode and the addressing electrodes described above; and control means for controlling the sequence of supplying the reset discharge pulse, the addressing pulse and the sustain discharge pulse:
When the odd-numbered field and the even-numbered field are switched over to each other, the control means executes a control so that the whole surface write discharge can be effected by applying a reset discharge pulse having a voltage higher than the discharge start voltage in the pair of the sustain electrode and the scan electrode that has executed, or is to execute, the sustain discharge, a self-erase discharge is effected at the point of time in which the reset discharge pulse having the voltage higher than the discharge start voltage is removed, a voltage having a polarity opposite to that of the voltage of the whole surface write discharge and approximate to the voltage of the sustain discharge pulse is applied for a period at least equal to the width of the sustain discharge pulse; and in the next odd-numbered field or the even-numbered field, the control means executes its control so that the whole surface write discharge can be effected in the pair of the sustain electrode and the scan electrode by applying the reset discharge pulse having a voltage higher than the discharge start voltage, and the self-erase discharge can be effected at the point of time in which the reset discharge pulse having a voltage higher than the discharge start voltage is eliminated.
According to the method for driving the plasma display panel and the apparatus for driving the same in the present invention, the reset discharge is executed by applying the voltage higher than the discharge start voltage to only the discharge cell that has executed the sustain discharge and the discharge cells adjacent to the former discharge cell for the period for starting the discharge when the interlace system driving sequence is executed, and the auxiliary erase pulse having a gentle slope is used thereafter to reliably eliminate the wall charges remaining between the sustain electrodes and the scan electrodes to zero, so that the erase discharge can be carried out mainly in the discharge cells that have executed the sustain discharge and in some case, in the discharge cells adjacent to the former discharge cells, too. Because the discharge is not effected for other discharge cells that do not effect the sustain discharge, on the other hand, stable driving can be accomplished with an improved contrast ratio.
When the odd-numbered fields and the even-numbered fields are switched over to each other in executing the interlace system driving sequence in the method for driving the plasma display panel and the apparatus for driving the same according to the present invention, the similar discharge is executed for the fields before switching, before the whole surface write discharge and the self-erase discharge are effected for the fields after switching of the fields, and thereafter the sustain discharge pulse is applied in the polarity opposite to that of the whole surface write pulse. Therefore, the reset discharge and the addressing discharge after switching of the fields can be executed stably.